Crystal Equation
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https://www.crystalequation.com
https://www.crystalequation.com
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Silicon DV Engineer V
Remote, CA 94023 US
Posted: 02/23/2023
2023-02-23
2023-04-27
Job Number: 37023
Job Description
Pay range is $99 - $117 per hour with full benefits available, including paid time off, medical/dental/vision/life insurance, 401K, parental leave, and more. Our compensation reflects the cost of labor across several US geographic markets. Pay is based on several factors including market location and may vary depending on job-related knowledge, skills, and experience.
THE PROMISES WE MAKE:
At Crystal Equation, we empower people and advance technology initiatives by building trust. Your recruiter will prep you for the interview, obtain feedback, guide you through any necessary paperwork and provide everything you need for a successful start. We will serve to empower you along the way and provide the path for your professional journey
Silicon DV Engineer V
Job Responsibilities:
Must Have:
THE PROMISES WE MAKE:
At Crystal Equation, we empower people and advance technology initiatives by building trust. Your recruiter will prep you for the interview, obtain feedback, guide you through any necessary paperwork and provide everything you need for a successful start. We will serve to empower you along the way and provide the path for your professional journey
Silicon DV Engineer V
Job Responsibilities:
- Achieve 100% functional and code coverage through analysis, test writing, and exclusions
- Automate code generation for testbench using scripts
- Monitor, delegate, and debug nightly test regression failures
- Functional verification and performance validation of performance-related design areas
- Support integration of IP block tests into larger SubSystem or SoC environment tests
- Implement and maintain testbench and scoreboards / checkers.
- Implement test sequences as per plan and debug failures
Must Have:
- 7+ years of proven experience as a DV engineer
- Hands on experience with executable test plans and coverage driven verification
- Hands on experience with SV (SystemVerilog) and UVM (Universal Verification Methodology or equivalent)
- Hands on Experience with Synopsys VCS / Verdi or Cadence Incisive tools
- 2+ Years of experience with C/C++
- 4+ Years of experience with a scripting language (Python or Perl)
- Experience in GPU, Display, or Imaging Pipeline Silicon development.
- Experience in development System Verilog UVM testbench environment from scratch
- Experience with Software/Hardware Co-simulation (DPI/VPI)
- Experience with C/C++ modeling of the Hardware Systems
- Experience with verification of high speed interfaces like MIPI
- Experience with on-chip bus protocols (AXI, AXI-Lite, AHB, OCP)
- Experience with post-silicon lab/bench test/validation
- Experience with UPF based simulation flow
- Must Have: Bachelor degree in Electrical/Computer Engineering or Computer Science
- Master's Degree preferred but not required