Crystal Equation
http://cdn.haleymarketing.com/templates/61283/logos/crystalequation-socialmedia.png
https://www.crystalequation.com
https://www.crystalequation.com
true
Pay range is $54 - $59 per hour with full benefits available, including paid time off, medical/dental/vision/life insurance, 401K, parental leave, and more. Our compensation reflects the cost of labor across several US geographic markets. Pay is based on several factors including market location and may vary depending on job-related knowledge, skills, and experience.
THE PROMISES WE MAKE:
At Crystal Equation, we empower people and advance technology initiatives by building trust. Your recruiter will prep you for the interview, obtain feedback, guide you through any necessary paperwork and provide everything you need for a successful start. We will serve to empower you along the way and provide the path for your professional journey.
Silicon Performance Modeling Engineer III
Role:
Duties:
Must have skills:
Education:
Silicon Performance Modeling Engineer III
300 West 6th Street Austin, TX 78701 US
Posted: 03/09/2023
2023-03-09
2023-04-27
Job Number: 37124
Job Description
Pay range is $54 - $59 per hour with full benefits available, including paid time off, medical/dental/vision/life insurance, 401K, parental leave, and more. Our compensation reflects the cost of labor across several US geographic markets. Pay is based on several factors including market location and may vary depending on job-related knowledge, skills, and experience.
THE PROMISES WE MAKE:
At Crystal Equation, we empower people and advance technology initiatives by building trust. Your recruiter will prep you for the interview, obtain feedback, guide you through any necessary paperwork and provide everything you need for a successful start. We will serve to empower you along the way and provide the path for your professional journey.
Silicon Performance Modeling Engineer III
Role:
- The ideal candidate will contribute to performance modeling, RTL-perf model correlation, workload profiling, silicon measurement and analysis efforts.
- Having strong background in SoC micro-architecture [CPU, Fabric, DRAM, Accelerators] is highly desired.
- Successful candidates are motivated self-starters who are comfortable operating in a cross-functional environment, and have a hands-on approach to problem-solving.
Duties:
- Performance modeling of IP components and modeling of SoC fabric and DRAM
- Profile and extract system-usage behavior of workloads and design micro-benchmarks
- Pre-silicon/post-silicon performance measurement, correlation and analysis
- Identify and evaluate firmware/software optimization opportunities and solidify HW-SW co-design
- Develop regression infrastructure and dashboarding capabilities
Must have skills:
- Experience with performance modeling and analysis for networks on chip (NoCs)
- Understanding of SoC Architecture, NoCs, memory sub-system, Quality of Service (QoS), and heterogeneous compute principles.
- Ability to deconstruct a problem, design experiments, analyze/visualize data and draw conclusions
- Experience with programming (C/C++, SystemC TLM2.0, Python), Assembly (e.g., Arm),scripting, automation and data visualization
- Understanding of basic power concepts and trade-offs
Education:
- Must Have: Bachelor degree in Electrical/Computer Engineering or Computer Science
- Master’s/PhD Degree preferred but not required